The use of silicon-on-insulation architecture (SOI) for high temperature operation of a pressure transducer is depicted in U.S. Pat. No. 7,231,828 entitled High Temperature Pressure Sensing System issued on Jun. 14, 2007 to A. D. Kurtz et al and assigned to Kulite Semiconductor Products Inc., the assignee herein. In that patent, there is disclosed a high temperature pressure sensing system including a pressure transducer. The system includes a pressure sensing piezoresistive sensor formed by a silicon-on-insulator (SOI) process. There is a SOI amplifier circuit which is coupled to the piezoresistive sensor, a SOI gain controller circuit, including a plurality of resistances that when selectively coupled to the amplifier, adjusts the gain. There is a plurality of off chip contacts corresponding to the resistors respectively, for electrically activating the corresponding resistors and using a metallization layer for the SOI sensor and SOI ASIC suitable for high temperature interconnections wherein the piezoresistive sensor amplifier circuit and gain control circuit are suitable for use in environments having a temperature greater than 175° C. and reaching between 250° C. and 300° C. Thus in the above noted patent namely U.S. Pat. No. 7,231,828 there is a described a SOI or silicon-on-insulator structure which employs a SOI pressure sensor device.
As is clear from the above-noted patent, by utilizing such devices, one can achieve high temperature operation and for example, operation in temperature ranges greater than 175° C. The above-noted patent describes various techniques utilized for providing SOI CMOS structures where the components are N-channel and P-channel transistors, diodes, capacitors and so on. Basically the fabrication process consists of producing a thin, single crystalline layer of silicon separated from the substrate via a high quality silicon dioxide or SiO2 layer. This can be done by using an oxygen implantation approach where the implanted oxygen creates an insulating silicon dioxide layer some distance from the top surface establishing a thin silicon layer isolated from the substrate. This can also be produced by fusion bonding an oxidized substrate wafer to a second wafer followed by selective etching of the second wafer to leave only a thin, high quality, layer of silicon over the SiO2 layer on the substrate. The process for the selective etching of the second silicon wafer can use either a conductivity selective etching process or a lap and polish process or a hydrogen implant and micro-splitting process. Once the silicon-on-insulator wafers are produced, selective doping and patterning, additional film growing and other semiconductor processing can be used to fabricate different features and components in the device. With controlled doping, the appropriate drain and source regions in the respective transistors are provided. A high quality oxide layer is then grown to serve as a gate oxide, over which a poly-crystalline P-type silicon will be deposited to act as a gate material. The same poly-crystalline material can also be used to form resistors as well as other components utilized in the chip. In this process, unlike bipolar technology where NI-CR having very low thermal temperature coefficient of resistance typically are used, resistors can not be made as metal layers. As a result, the utilized poly-crystalline resistors have a relatively large TCR of about 1500 ppm/0° C. orders of magnitude higher than that of the metal film resistors. With the SOI approach, all associated components are dielectrically isolated from each other and from the substrate, thus eliminating the effects of leakage currents and substrate parasitic capacitance. The use of SOI enables the fabrication of very stable devices operational up to and above 300° C. and suitable for high voltage and low voltage applications. This technology has been explained in detail in the above-noted patent, namely U.S. Pat. No. 7,231,828 which is incorporated herein in its entirety. In any event, that patent describes in detail the advantages of SOI technology in providing sensor devices.
It is an object of the present invention to provide circuitry which adds significant capabilities to the operation of pressure transducers while maintaining high temperature operations and so on. As indicated above, the above-noted patent, namely U.S. Pat. No. 7,231,828 depicts the implementation and advantages gained by using a SOI sensor with SOI electronics. In this manner, one can implement a transducer with a high level output capable of operating at temperatures in excess of 250° C. and potentially up to 300° C. The circuit to be described uses analog components as well as digital components. The analog components, for example, may be operational amplifiers and regulators. Thus, as will be shown, the present invention includes further enhancements of the electronic circuit with significant advantages. The enhancements disclosed here are digital circuits which add significant capabilities to the operation of the transducer, while maintaining the capability of operation at high temperatures of +250° C. and even up to 300° C. This feature is possible due to the dielectric isolation of each device in the SOI chip which eliminates leakage currents. The leakage currents are the major factor limiting the operation of circuits using conventional technologies.